A typical image sensor senses light by converting impinging photons into electrons that are integrated (collected) in sensor pixels. After completion of integration cycle, charge is usually transported, using the charge coupled device (CCD) process, into an on-chip analog memory and from the memory it is scanned into an output amplifier that is located adjacent to the pixel array. The signal from each pixel is processed in a serial fashion through the same amplifier, which results in high pixel-to-pixel uniformity, however the amplifier requires high speed. With increasing array size the pixel size, and consequently, the amount of signal in each pixel is reduced while the speed increases. This places more stringent demands on performance of the charge detection amplifiers that need to have higher sensitivity (conversion gain), lower noise, and operate at higher speeds. A typical charge detection amplifier consists of a floating diffusion that is reset by a reset transistor and that is connected to a gate of a Source Follower (SF) that is typically an NMOS transistor. More details about such circuits can be found for example in the book: Albert J. P. Theuwissen “Solid-State Imaging with Charge-Coupled Devices” Kluwer Academic Publishers, Boston 1995 pp.76-79, or in the article: J. Hynecek “Design and Performance of a Low-Noise Charge Detection Amplifier for VPCCD Devices”, IEEE Transactions on Electron Devices, vol. ED-31, No. 12 Dec. 1984. When charge is transferred on the floating diffusion the transistor senses the resulting potential change and this change is then transferred either directly to the output terminals of the chip or to other on on-chip signal processing circuits. When the signal is transferred directly to the output terminals another buffer SF is usually necessary to increase the chip output driving power. For achieving a high conversion gain the first SF stage needs to be very small in order not to load the FD charge detection node by excessively large transistor gate input capacitance. The small transistor size also increases noise. On the other hand, for high frequency operation, it is necessary that the first SF stage has a reasonable size to drive the large input capacitance of the next stages with high speed. These are contradictory requirements that can be solved, for example, by using three SF stages. However, this solution results in an unacceptable loss of voltage signal and the resulting sensor charge conversion factor and thus overall sensor sensitivity.